The present disclosure relates generally to integrated circuits, such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to providing a processor-based control interface for designing partial-reconfiguration (PR) regions and associated PR personas, such that recompilation of personas and/or static logic may be reduced.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits are used in numerous electronic devices and for numerous purposes. Some integrated circuits include programmable logic, such as field programmable gate array (FPGA) fabric, that can be programmed to support a variety of circuit designs after manufacturing. These programmable logic devices may contain programmable logic circuitry that can be programmed to perform a variety of functions.
Some programmable logic devices support a form of programming referred to as “partial reconfiguration.” Partial reconfiguration involves programming an initial programmable logic design into the programmable logic device that can be rapidly reconfigured during runtime. Thus, while the initial programmable logic design may take a substantial amount of programming time (e.g., on the order of hours), partial reconfiguration during runtime may be faster (e.g., on the order of seconds). The initial programmable logic design may include a number of logic elements that can be rapidly reprogrammed during runtime. This allows the initial programmable logic design to support many different partial reconfiguration implementations, known as “personas,” to be rapidly reprogrammed during runtime.
Thus, partial reconfiguration allows a programmable logic device to switch personas faster than the time it would take to fully reprogram the programmable logic device with a new initial programmable logic design. Despite this, even the short time involved in switching personas may present undesirable latency for some use cases. The impact of this latency may be compounded for use cases that involve switching personas relatively often.